121 lines
4.8 KiB
Diff
121 lines
4.8 KiB
Diff
From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
Date: Thu, 21 Sep 2023 16:15:16 +0200
|
|
Subject: [PATCH 5/5] drm/amd/display: Move the memory allocation out of
|
|
dcn20_validate_bandwidth_fp().
|
|
Origin: https://www.kernel.org/pub/linux/kernel/projects/rt/6.6/older/patches-6.6.7-rt18.tar.xz
|
|
|
|
dcn20_validate_bandwidth_fp() is invoked while FPU access has been
|
|
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
|
|
It is not possible to allocate memory with disabled preemption even with
|
|
GFP_ATOMIC on PREEMPT_RT.
|
|
|
|
Move the memory allocation before FPU access is enabled.
|
|
To preserve previous "clean" state of "pipes" add a memset() before the
|
|
second invocation of dcn20_validate_bandwidth_internal() where the
|
|
variable is used.
|
|
|
|
Link: https://lore.kernel.org/r/20230921141516.520471-6-bigeasy@linutronix.de
|
|
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
|
|
---
|
|
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 10 +++++++++-
|
|
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 16 +++++++---------
|
|
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h | 5 ++---
|
|
3 files changed, 18 insertions(+), 13 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
|
|
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
|
|
@@ -2141,9 +2141,17 @@ bool dcn20_validate_bandwidth(struct dc
|
|
bool fast_validate)
|
|
{
|
|
bool voltage_supported;
|
|
+ display_e2e_pipe_params_st *pipes;
|
|
+
|
|
+ pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
|
|
+ if (!pipes)
|
|
+ return false;
|
|
+
|
|
DC_FP_START();
|
|
- voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
|
|
+ voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate, pipes);
|
|
DC_FP_END();
|
|
+
|
|
+ kfree(pipes);
|
|
return voltage_supported;
|
|
}
|
|
|
|
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
|
|
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
|
|
@@ -1910,7 +1910,7 @@ void dcn20_patch_bounding_box(struct dc
|
|
}
|
|
|
|
static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
|
|
- bool fast_validate)
|
|
+ bool fast_validate, display_e2e_pipe_params_st *pipes)
|
|
{
|
|
bool out = false;
|
|
|
|
@@ -1919,7 +1919,6 @@ static bool dcn20_validate_bandwidth_int
|
|
int vlevel = 0;
|
|
int pipe_split_from[MAX_PIPES];
|
|
int pipe_cnt = 0;
|
|
- display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
|
|
DC_LOGGER_INIT(dc->ctx->logger);
|
|
|
|
BW_VAL_TRACE_COUNT();
|
|
@@ -1954,16 +1953,14 @@ static bool dcn20_validate_bandwidth_int
|
|
out = false;
|
|
|
|
validate_out:
|
|
- kfree(pipes);
|
|
|
|
BW_VAL_TRACE_FINISH();
|
|
|
|
return out;
|
|
}
|
|
|
|
-bool dcn20_validate_bandwidth_fp(struct dc *dc,
|
|
- struct dc_state *context,
|
|
- bool fast_validate)
|
|
+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
|
|
+ bool fast_validate, display_e2e_pipe_params_st *pipes)
|
|
{
|
|
bool voltage_supported = false;
|
|
bool full_pstate_supported = false;
|
|
@@ -1982,11 +1979,11 @@ bool dcn20_validate_bandwidth_fp(struct
|
|
ASSERT(context != dc->current_state);
|
|
|
|
if (fast_validate) {
|
|
- return dcn20_validate_bandwidth_internal(dc, context, true);
|
|
+ return dcn20_validate_bandwidth_internal(dc, context, true, pipes);
|
|
}
|
|
|
|
// Best case, we support full UCLK switch latency
|
|
- voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
|
|
+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
|
|
full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
|
|
|
|
if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
|
|
@@ -1998,7 +1995,8 @@ bool dcn20_validate_bandwidth_fp(struct
|
|
// Fallback: Try to only support G6 temperature read latency
|
|
context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
|
|
|
|
- voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
|
|
+ memset(pipes, 0, dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st));
|
|
+ voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false, pipes);
|
|
dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
|
|
|
|
if (voltage_supported && (dummy_pstate_supported || !(context->stream_count))) {
|
|
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
|
|
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
|
|
@@ -61,9 +61,8 @@ void dcn20_update_bounding_box(struct dc
|
|
unsigned int num_states);
|
|
void dcn20_patch_bounding_box(struct dc *dc,
|
|
struct _vcs_dpi_soc_bounding_box_st *bb);
|
|
-bool dcn20_validate_bandwidth_fp(struct dc *dc,
|
|
- struct dc_state *context,
|
|
- bool fast_validate);
|
|
+bool dcn20_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
|
|
+ bool fast_validate, display_e2e_pipe_params_st *pipes);
|
|
void dcn20_fpu_set_wm_ranges(int i,
|
|
struct pp_smu_wm_range_sets *ranges,
|
|
struct _vcs_dpi_soc_bounding_box_st *loaded_bb);
|